CSE
565
|
Digital
Design Test and Verification – Spring 2008 Syracuse
University L.C. Smith College of Engineering and Computer Science |
Description
|
Techniques
for validating the correctness of the logical and physical implementation of
a digital system in two independent modules: (1) functional verification, and
(2) test and validation. |
Instructor
|
Dr.
eercanli@syr.edu. CST 4-297.
443-3564. Office hours: TTh 11:30am-1:30pm. |
TA
|
Jean
Hannouche. jhannouc@syr.edu. |
Times
|
W
5:15-7:45pm at CST 3-212. |
Textbook
|
Comprehensive
Functional Verification-The Complete Industry Cycle B.
Wile, J. Goss, W. Roesner, MKP, 2005. |
Reference
|
Essentials of
Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits M.
L. Bushnell and V. D. Agrawal, Springer, 2005. |
Prerequisites
|
CSE 464 and CSE 561. |
Grading
|
The
course grade will be based on the quality of the designs, the design reports
and presentations, and the exams. Assignments and Lab Projects: 40%, Three Exams:
60%. |
Homework
|
Homework
and project assignments are to be submitted in lecture on the assigned due
date. No late assignments will be accepted. You are expected to complete the
homework individually. However, you can discuss assignments and solutions
with each other, but all work submitted must be the sole work of the author.
Course projects will be completed individually or in-groups of two. Answers
to selected problems will be available on the class web page. |
Exams
|
All exams must be taken at the scheduled time unless a previous
arrangement (with a good reason) has been made with the instructor. |
Attendance
|
You are expected to attend each class punctually and remain for
the entire class period; tardiness disturbs everyone. You need to inform the
instructor in advance if you expect to miss a class or leave the course
before the end of the semester. If you miss class your absence will be
excused by the instructor only if a doctor's certificate or other evidence is
submitted. If you have been absent and fail to submit an excuse to the
instructor, your absence will be considered unexcused. Even if your absence
is excused, you remain responsible for the work associated with the class you
missed. There will be a number of unannounced pop quizzes. |
Academic Honesty
|
Cheating in any form is not tolerated, nor is assisting another
person to cheat. The submission of any work by a student is taken as a
guarantee that the thoughts and expressions in it are the student's own
except when properly credited to another. Violations of this principle include giving or receiving aid in
an exam or where otherwise prohibited, fraud, plagiarism, the falsification
or forgery of any record, and any other deceptive act in connection with
academic work. Plagiarism is the representation of another's words, ideas,
programs, formulae, options, or other products of work as one's own, either
overtly or by failing to attribute them to their true source. Always protect your own work from others, since it is often not
possible to determine who the originator or the copier was. Such offense will
result in a failing grade ‘F’ and a letter of reprimand in your
permanent student file. |
Course Outline
|
H1
due on Feb 6. P1
due on Feb 13. H2 due
on Feb 27. P2 due
on Mar 5. P3 due
on Mar 26. 1. Introduction
to Verification and Testing 2. Verification
flow and planning 3. Simulation-based
verification 4. HDL testbench design techniques 5. Verification
languages, verification coverage 6. Intro
to Formal verification 7. Stimulus
generation strategies 8. Intro
to Testing of VLSI Systems 9. Fault
modeling and fault detection 10. Testing
for stuck-at faults and ATPGs 11. Memory
test, density and defect trends 12. Design
for testability and Built-In Self-Test 13. Industrial
perspectives and Case Studies |
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CSE 565 |
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