CSE 561

Digital Machine Design - Fall 2009

Syracuse University L.C. Smith College of Engineering and Computer Science

Description

Behavioral and structural design methods and examples using a hardware description language (VHDL).  Control, arithmetic, bus systems, memory systems.  Logic synthesis from hardware language descriptions.

Instructor

Dr. Ehat Ercanli. CST 4-297. eercanli@syr.edu. 443-3564. Office Hours: T TH 3:00-4:00 pm.

TA

Mubarek Mohammed. CST 0-124. mmohamme@syr.edu.

Times

T TH 9:30-10:50am at SciTech CST 3-216.

Help Sessions

W 5:00-7:00 pm, TH 11:00 am - 1:00 pm at SUN/Synopsys Charles Babbage Lab, CST 1-214.

Textbook

The Designer's Guide to VHDL by Peter Ashenden, Morgan Kaufmann, 3rd edition, 2008.

Reference

Embedded Systems Architecture by T. Noergaard, Elsevier, 2005.

Prerequisites

CSE 261 and programming competence

Grading

The course grade will be based on the quality of the designs, the design reports and presentations, and the exams.

Assignments/Lab Projects: 50%, Three Exams: 50%.

Homework

Homework assignments are to be submitted in lecture on the assigned due date. No late assignments will be accepted. You are expected to complete the homework individually. However, you can discuss assignments and solutions with each other, but all work submitted must be the sole work of the author. Course projects will be completed individually or in-groups of two. Answers to selected problems will be available on the class web page.

Exams

All exams must be taken at the scheduled time unless a previous arrangement (with a good reason) has been made with the instructor.

WWW

Our class web page will be updated frequently with lecture slides (when possible), homework assignments and solutions, and tests and solutions, and more interesting stuff.

Attendance

You are expected to attend each class punctually and remain for the entire class period; tardiness disturbs everyone. You need to inform the instructor in advance if you expect to miss a class or leave the course before the end of the semester. If you miss class your absence will be excused by the instructor only if a doctor's certificate or other evidence is submitted. If you have been absent and fail to submit an excuse to the instructor, your absence will be considered unexcused. Even if your absence is excused, you remain responsible for the work associated with the class you missed.  There will be a number of unannounced pop quizzes.

Academic Honesty

Cheating in any form is not tolerated, nor is assisting another person to cheat. The submission of any work by a student is taken as a guarantee that the thoughts and expressions in it are the student's own except when properly credited to another.

Violations of this principle include giving or receiving aid in an exam or where otherwise prohibited, fraud, plagiarism, the falsification or forgery of any record, and any other deceptive act in connection with academic work. Plagiarism is the representation of another's words, ideas, programs, formulae, options, or other products of work as one's own, either overtly or by failing to attribute them to their true source.

Always protect your own work from others, since it is often not possible to determine who the originator or the copier was. Such offense will result in a failing grade ‘F’ and a letter of reprimand in your permanent student file.

Required Knowledge and Skills

Recall:

1. You should be able to explain Boolean algebra and the design methods such as Combinational logic design and Sequential machine design.

Comprehension:

2. You should be able to translate between various formal representations for design and analysis, (e.g., translate state tables into a schematic of registers and logic, translate logic schematics into logic functions, etc.) and interpret the meaning of the various formal representations.

3. When given an abstract description or model of a component or system, you should be able to translate the description into an alternative abstract description or model.

Application:

4. When given English language descriptions of behavior, you should be able to translate them into the appropriate specification such as a Boolean equation or a state transition diagram.

5. When given a formal model specifying the behavior of a component or system such as a finite-state machine specification, you should be able to refine it into an implementation consisting of registers and combinational logic.

Acquired Knowledge and Skills

Recall:

1. You should be familiar with design automation tools to realize the given specifications such as Modeltech for simulation and Synopsys for both simulation and synthesis.

Comprehension:

2. When given an abstract description or model of a component or system, you should be able to translate the description into an alternative abstract description or model.

3. You should become proficient in a hardware-description language (HDL) ¾ VHDL used in this class to simulate and to synthesize digital designs.

Application

4. When given English language descriptions of behavior, you should be able to do system level designs by

· Mastering design issues in a bottom-up fashion and

· Designing systems for specific applications in a top-down methodology recognizing the differences between:

- Behavioral and Structural approaches

- Simulation and Synthesis of digital designs

- Controlpath and Datapath designs.

Synthesis:

5. You should be able to produce working digital designs that meet design specifications.

6. When given an abstract description of behavior, you should be able to create a concrete implementation that is a faithful refinement of the specification.

Evaluation:

7. When given a VHDL model and a set of specifications, you should be able to instrument the hardware to judge whether it meets its specification.

8. You should be able to judge the degree of correspondence between abstract behavioral specifications and the actual behavior of implementations.

9. When given a specification and its VHDL implementation, you should be able to evaluate whether the implementation is correct with respect to its specification and meets performance requirements.

10. When given an implementation and its specifications and requirements, you should be able to evaluate the quality and thoroughness of the tests themselves and the test results.

Tentative Course Schedule

	Tuesday	Thursday
09-01	Introduction.	Design Methodology and Alternatives.
09-08	Embedded systems.	Specifications. Partitioning. HW1 (due 9/17). Cover Sheet.
09-15	Tutorial at Synopsys/Babbage Lab.	Basics and Samples. Simulation modeling.
09-22	Combinational logic.	Sequential logic.
09-29	State machine design. Test benches.	Timing models. Example. HW2 (due 10/15).
10-06	Examples.	Generating outputs.
10-13	Review.	Exam 1.
10-20	Hierarchical Design. CPU example.	High Level Synthesis. HW3 (due 11/03).
10-27	VHDL Synthesis Guidelines.	Synthesis Tutorial at the Lab.
11-03	Synthesis	Optimization Techniques.
11-10	Coding Style. HW4 (due 11/24).	High-Level Synthesis.
11-17	Verification.	Assertion-based verification.
11-24	Verilog basics and sample codes.	Thanksgiving. No Classes.
12-01	Verilog Examples.	Technology. Tutorial at Synopsys/Babbage Lab.
12-08	Review and Future Trends.	Exam 2.
	Textbook Resources. OpenCores. EDA Resource. VHDL FAQ. Discussion on Synthesis. Discussions on VHDL. A Verilog Tutorial. News. ChipDesign. Intel. UltraSparc. HP/Alpha. IBM PowerPC. ARM. Freescale.	GRADES. (Updated: 11/09).

CSE 561